1. Field of the Invention
The present invention relates to the provision of device isolation structures between devices of an integrated circuit formed in and on a semiconductor substrate and to the use of chemical mechanical polishing techniques in the formation of shallow trench isolation structures.
2. Description of the Related Art
A variety of integrated circuits incorporate device isolation structures between adjacent semiconductor devices to prevent carriers from traveling through the substrate between the adjacent devices. For example, device isolation structures are conventionally formed between adjacent field effect transistors (FETs) in dense semiconductor circuits such as dynamic random access memories (DRAMs) to reduce charge leakage to and from the charge storage nodes of the FETs. Often, device isolation structures take the form of thick field oxide regions extending below the surface of the semiconductor substrate. The most common early technique for forming a field oxide region is the local oxidation of silicon ("LOCOS") technique. The LOCOS technique, including the various modified LOCOS procedures that have been introduced over the years, have provided effective device isolation at a relatively low cost and with an acceptable level of reliability. The LOCOS technique has various drawbacks, however, including its well known problems related to stress generation and the thin "bird's beak" region formed at the periphery of the LOCOS field isolation structure. Particularly because of the bird's beak problem, the LOCOS field isolation structure is difficult to implement effectively for small device geometries and so must be replaced in high density devices by a more readily scaled device isolation region.
Shallow trench isolation ("STI") has become a prevalent strategy for device isolation. In STI, a sharply defined trench is formed in the semiconductor substrate by anisotropic etching, sometimes using a silicon nitride hard mask much like the mask used for LOCOS processing. The trench is then filled with oxide to provide a device isolation region having an upper surface near or at the original substrate surface. After formation of the shallow trench isolation structure, devices are provided in and on the P-type surface of the typical silicon substrate. One or more FET devices might be formed adjacent the sides of the STI structure, with each FET including a pair of N-type source/drain regions on either side of a channel region of the FET and a polysilicon gate electrode separated from the corresponding channel region by a gate oxide layer. The shallow trench isolation structure separates the source/drain regions of the FET device from other doped regions in adjacent regions of the substrate. Shallow trench isolation structures provide effective isolation across their entire width and are readily scaled to small device geometries. In this regard, shallow trench isolation structures are unlike LOCOS isolation regions, which must accommodate the characteristic LOCOS bird's beak structures on either side of the LOCOS isolation region and so do not provide effective device isolation over their entire width. In addition, the techniques typically used to form shallow trench isolation structures naturally produce a substantially planarized surface over the isolation structure, which is advantageous for almost all subsequent steps in the process flow. Formation of a shallow trench isolation structure is now discussed in greater detail with reference to FIGS. 1-4.
FIG. 1 illustrates an early stage in the formation of an integrated circuit device and illustrates a small portion of the device substrate where a shallow trench isolation structure is to be formed. Silicon substrate 10 is coated with a layer of silicon nitride 12, for example by chemical vapor deposition (CVD), which will be used as a polish stop layer for a chemical mechanical polishing process used in forming the shallow trench isolation structure. Next, a trench definition mask 14 is formed by spinning on and curing a layer of photoresist on the silicon nitride layer 12 and then exposing and selectively removing the photoresist layer to form an opening 16 in the photoresist mask 14. A trench is formed in the substrate by etching through the silicon nitride layer 12 and then etching a trench 18 into the silicon substrate 10 (FIG. 2). As is illustrated, the etching processes used to etch through the silicon nitride layer 12 and to open the trench tend to erode the photoresist mask during the etching process so that the trench produced in this process has slightly sloped sidewalls. The trench etching mask 14 is then removed.
Next, the trench 18 is filled with a layer of silicon oxide 20, for example, by atmospheric pressure chemical vapor deposition (APCVD) using tetraethylorthosiloxane (TEOS) as a source gas. The trench is conventionally overfilled during deposition, as shown in FIG. 3, because TEOS oxide typically requires a densification process and the TEOS oxide layer shrinks during densification. Densification of the TEOS oxide is accomplished at a temperature of approximately 1000.degree. C. for a time period of about 10-30 minutes. After densification, the portion of the TEOS oxide layer extending above the silicon nitride layer 12 is removed by chemical mechanical polishing using the silicon nitride layer 12 as a stop for the polishing process, leaving an oxide plug 22 in the trench region (FIG. 4).
As shown in FIG. 4, the surface of the oxide plug 22 is typically recessed below the surface of the silicon nitride polish stop layer 12, as indicated by 24 in FIG. 4, during chemical mechanical polishing because the oxide plug is softer and polishes more rapidly than the silicon nitride layer. The silicon nitride layer 12 is next removed from over the substrate, typically leaving a portion of the oxide plug 22 extending above the surface of the substrate. A hydrofluoric acid dip is used to remove a thickness of the oxide plug 22 and to clean the surface of the substrate 10. Often, the oxide etching and other processing steps (not illustrated) can cause a sufficient amount of the plug oxide 22 to be etched so that the surface of the plug oxide is recessed below the surface of the substrate 10. The overetching condition may be most pronounced at the edges of the oxide plug 34 immediately adjacent the surface of the substrate 10, or the entire surface of the oxide plug may be recessed substantially uniformly below the surface of the substrate. In either case, overetching may cause a "shoulder" portion of the substrate to be exposed and partially etched at the side wall of the trench, or only a thin layer of oxide may cover the substrate adjacent the side wall of the trench.
After the plug oxide is defined within the shallow trench isolation structure, a gate oxide layer is next grown thermally over the exposed active device surfaces of the substrate. As a practical matter, the gate oxide layer often is of poor quality with a convex profile at the "shoulder" region of the substrate at the edge the trench of the shallow trench isolation structure. Subsequent formation of gate electrodes and wiring lines that extend over the edges of the trenches are then separated from the substrate at the edge of the trench by an oxide layer that has poor insulating properties. The poor qualities of the oxide layer may mediate a coupling between the gate electrodes or wiring lines and the substrate covered by the poor quality oxide layer formed over the trench shoulder regions. This undesirable coupling may be sufficient to allow for parasitic MOSFET action at the shoulder region, with the wiring line 44 acting as part of the gate of the parasitic MOSFET and signals on the wiring line controlling action of the parasitic MOSFET. The formation of parasitic MOSFETs or other forms of electrical coupling between the wiring line and the substrate can reduce the turn-on threshold voltage of the transistor channel and can produce the abnormal subthreshold current associated with the "kink" effect. Occurrence of the kink effect impairs device and circuit performance and is consequently undesirable.